User manual ABIT AT8 32X

[. . . ] AT8 32X AMD Athlon 64x2/64FX/64 System Board Socket 939 User's Manual 4310-0000-14 Rev. 2. 00 Copyright and Warranty Notice The information in this document is subject to change without notice and does not represent a commitment on part of the vendor, who assumes no liability or responsibility for any errors that may appear in this manual. No warranty or representation, either expressed or implied, is made with respect to the quality, accuracy or fitness for any particular part of this document. In no event shall the manufacturer be liable for direct, indirect, special, incidental or consequential damages arising from any defect or error in this manual or product. [. . . ] Advanced Chipset Features Phoenix ­ AwardBIOS CMOS Setup Utility Advanced Chipset Features DRAM Configuration Press Enter LDT & PCI Bus Control Press Enter System BIOS Cacheable Enabled Item Help :Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults DRAM Configuration: Click <Enter> key to enter its submenu: Phoenix ­ AwardBIOS CMOS Setup Utility DRAM Configuration DRAM Timing Selectable Auto - DRAM Clock Auto - CAS Latency Time Auto - Row Cycle Time Auto - Row Refresh Cycle Time Auto - Min RAS# Active Time Auto - RAS# to CAS# Delay Auto - RAS# Precharge Time Auto - RAS# to RAS# Delay Auto - Write Recovery Time Auto - Write to Read Delay Auto - Read to Write Delay Auto - DRAM Command Rate Auto - Bank Interleaving Enabled - Burst Length 4 beats 32 bit Dram Memory Hole Auto MTRR Mapping Mode Continuous DRAM ECC Feature Control Non-ECC - ECC Memory Interlock At Least One - ECC MCE Enable Disabled - Chip-Kill Mode Enable Disabled - ECC Redirection Disabled - DRAM Scrub Rate Disabled - L2 Cache Scrub Rate Disabled - DCache Scrub Rate Disabled Item Help X X X X X X X X X X X X X X X X X X X X X :Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults DRAM Timing Selectable: This item selects the DRAM timing mode. When set to "By SPD", the BIOS will read the DRAM module AT8 32X BIOS Setup 3-15 SPD data and automatically set to the values stored in it. The system may be unstable or unable to boot up if your DRAM module does not support the clock you set. When set to [By SPD], the BIOS will read the DRAM module SPD data and automatically set the DRAM clock by the value stored in it. CAS Latency Time: You can select SDRAM CAS (Column Address Strobe) latency time according your SDRAM specification. Row Cycle Time: This item specifies the RAS# active to RAS# active time or auto refresh time of the same bank. Row Refresh Cycle Time: This item specifies the auto refresh active to RAS# active time or RAS# auto refresh time. RAS# to CAS# Delay: This item specifies the RAS# active to CAS# read write delay time to the same bank. RAS# to RAS# Delay: This item specifies the RAS# active to RAS# active delay time of different bank. Write Recovery Time: This item specifies the time measured from the last write datum is safely registered by the DRAM. Write to Read Delay: This item specifies the time measured from the rising edge following the last non-masked data strobe to the rising edge of the next read command. DRAM Command Rate: When the host (northbridge) locates the desired memory address, it then processes the wait state of commands. Bank Interleaving: Depending on your SDRAM module structure, the 4-Way setting can offer the best performance. If you choose the wrong setting, the computer system will not run in a stable manner. For detailed information on your SDRAM module, please ask your SDRAM module manufacturer. User's Manual 3-16 Chapter 3 Burst Length DDR SDRAM modules provide a Burst mode that means an auto precharge function for programmable READ or WRITE burst lengths of 2, 4 or 8 locations. This means that if we set burst length to 8, the address bus will access 8 bytes each cycle to precharge, etc. 32 bit Dram Memory Hole: This item selects the method to remap the 32 bit Dram memory hole. The MTRR (Memory-Type and Range Registers) controls the access and cacheability of memory regions in the processor. DRAM ECC Feature Control When installed with the DRAM that support ECC feature, you may select [ECC] option, and then control the following sub-items. ECC Memory Interlock ECC MCE Enable Chip-Kill Mode Enable ECC Redirection DRAM Scrub Rate L2 Cache Scrub Rate DCache Scrub Rate AT8 32X BIOS Setup 3-17 Back to Advanced Chipset Features Setup Menu: LDT & PCI Bus Control: Click <Enter> key to enter its submenu: Phoenix ­ AwardBIOS CMOS Setup Utility LDT & PCI Bus Control LDT Configuration Enabled Upstream LDT Bus Width 16 bit Downstream LDT Bus Width 16 bit LDT Bus Frequency Auto PCIE Reset Delay Disabled Item Help :Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help F5: Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults LDT Configuration: This item enables or disables the LDT Configuration function. Upstream LDT Bus Width: This item sets the value for the Upstream LDT Bus Width. [. . . ] After all, your reseller regards you as an important customer who may purchase more products and who can urge your friends to buy from him or her as well. They should know best what your system configuration is and your problem. If you feel that you need to contact ABIT directly you can send email to the ABIT technical support department. First, please contact the support team for the branch office closest to you. [. . . ]